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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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SST49LF040 Fiches technique(PDF) 28 Page - Silicon Storage Technology, Inc |
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SST49LF040 Fiches technique(HTML) 28 Page - Silicon Storage Technology, Inc |
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28 / 48 page  28 Advance Information 4 Mbit LPC Flash SST49LF040 ©2001 Silicon Storage Technology, Inc. S71213-00-000 11/01 562 FIGURE 16: BLOCK-ERASE TIMING DIAGRAM (LPC MODE) 562 ILL F15.1 RST# LFRAME# LAD[3:0] 0000b 011Xb A[23:20] A[19:16] 0101b 0101b 0101b 1010b 0101b 1010b Tri-State TAR Load Address "YYYY 5555H" in 8 Clocks Write the 1st command to the device in LPC mode. Address1 1 Clock 1 Clock 1st Start Memory Write Cycle TAR Sync Data Start next Command 1 Clock 1 Clock 2 Clocks Load Data "AAH" in 2 Clocks 1111b 0000b LCLK RST# = VIH LFRAME# LAD[3:0] 0000b 011Xb A[23:20] A[19:16] 1010b 1010b 1010b 0101b 0010b 0101b Tri-State TAR Load Address "YYYY 2AAAH" in 8 Clocks Write the 2nd command to the device in LPC mode. Address1 1 Clock 1 Clock 2nd Start Memory Write Cycle TAR Sync Data Start next Command 1 Clock 1 Clock 2 Clocks Load Data "55H" in 2 Clocks 1111b 0000b LCLK RST# = VIH LFRAME# LAD[3:0] 0000b 011Xb A[23:20] A[19:16] 0101b 0101b 0101b 1000b 0101b 0000b Tri-State TAR Load Address "YYYY 5555H" in 8 Clocks Write the 3rd command to the device in LPC mode. Address1 1 Clock 1 Clock 3rd Start Memory Write Cycle TAR Sync Data Start next Command 1 Clock 1 Clock 2 Clocks Load Data "80H" in 2 Clocks 1111b 0000b LCLK RST# = VIH LFRAME# LAD[3:0] 0000b 011Xb A[23:20] A[19:16] 0101b 0101b 0101b 1010b 0101b 1010b Tri-State TAR Load Address "YYYY 5555H" in 8 Clocks Write the 4th command to the device in LPC mode. Address1 1 Clock 1 Clock 4th Start Memory Write Cycle TAR Sync Data Start next Command 1 Clock 1 Clock 2 Clocks Load Data "AAH" in 2 Clocks 1111b 0000b LCLK RST# = VIH LFRAME# LAD[3:0] 0000b 011Xb A[23:20] A[19:16] 1010b 1010b 1010b 0101b 0010b 0101b A[19:16] XXXXb XXXXb XXXXb 0101b BAX 0000b Tri-State TAR Load Address "YYYY 2AAAH" in 8 Clocks Load Block Address in 8 Clocks Write the 5th command to the device in LPC mode. Address1 1 Clock 1 Clock 5th Memory Write Cycle TAR Sync Data Start next Command 1 Clock 1 Clock 2 Clocks Load Data "55H" in 2 Clocks Load Data “50” in 2 Clocks 1111b 0000b LCLK RST# = VIH LFRAME# LAD[3:0] 0000b 011Xb A[23:20] Tri-State TAR Write the 6th command (target sector to be erased) to the device in LPC mode. BAX = Block Address Address1 1 Clock 1 Clock 6th Start Memory Write Cycle TAR Sync Data Internal erase start Internal erase start 1 Clock 2 Clocks 1111b 0000b CE# = VIL CE# = VIL CE# = VIL CE# = VIL CE# = VIL LCLK CE# A[31:28] A[27:24] A[31:28] A[27:24] A[31:28] A[27:24] A[31:28] A[27:24] A[31:28] A[27:24] A[31:28] A[27:24] Note: YYYY must be within memory address range specified in Figures 4 and 5. |
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