SST49LF040 datasheet(23/48 Pages) SST

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4 Mbit LPC Flash

SST49LF040

S71213-00-000

11/01 562

FIGURE 10: READ CYCLE TIMING DIAGRAM (LPC MODE)

FIGURE 11: WRITE CYCLE TIMING DIAGRAM (LPC MODE)

562 ILL F09.0

LCLK

RST#

CE#

LFRAME#

LAD[3:0]

0000b

010Xb

A[23:20] A[19:16]

A[3:0]

A[7:4]

A[11:8]

A[15:12]

1111b

Tri-State

2 Clocks

TAR

Load Address in 8 Clocks

Address

1 Clock 1 Clock

Start

Memory

Read

Cycle

TAR

1 Clock

Sync

Data

Next Start

Data Out 2 Clocks

1 Clock

0000b

D[7:4]

D[3:0]

0000b

TCYC

TVAL

TSU TDH

A[31:28] A[27:24]

562 ILL F10.0

RST#

LFRAME#

TCYC

LAD[3:0]

0000b

011Xb

A[23:20] A[19:16]

A[3:0]

A[7:4]

A[11:8]

A[15:12]

1111b

Tri-State

2 Clocks

TAR

Load Address in 8 Clocks

Address

1 Clock

Start

Memory

Write

Cycle

TAR

1 Clock

Sync

Data

Next Start

Load Data in 2 Clocks

1 Clock

0000b

D[7:4]

D[3:0]

0000b

TSU TDH

LCLK

CE#

A[31:28] A[27:24]

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