DM9621 datasheet(15/66 Pages) DAVICOM

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DM9621

USB2.0 to Fast Ethernet Controller

Preliminary

Version: DM9621 -14-DS-P02

February 23, 2011

4.2 Network Status Register (01H)

Bit

Name

Default

Description

SPEED

PHS0,R

Media Speed Status

0:100Mbps

1:10Mbps

This bit is no meaning when LINKST=0.

This bit read only in internal PHY mode and it can be written in external PHY mode.

This bit can also be forced by register 2EH bit 5 and 2.

LINKST

PHS0,R

Link status

0:link failed

1:link OK

This bit read only in internal PHY mode and it can be written in external PHY mode.

This bit can also be forced by register 2EH bit 5 and 0.

WAKEST

P0,W/C

Wakeup event status.

This bit is set when wakeup event status asserted.

This bit is cleared by write “1” or when wakeup mode disabled.

RESERVED

PHS0,R

Reserved

RESERVED

PHS0,

RW/C1

Reserved

RESERVED

PHS0,

RW/C1

Reserved

RXOV

PHS0,R

RX FIFO Overflow Status

This bit is set when RX FIFO free space is less than 544-byte

This bit be cleared when RX FIFO free space is more than 2K.

RXRDY

PHS0,R

RX Packet Ready

This bit is set when there are one or more packets in RX FIFO.

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