Functional description

STV7623

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Doc ID 018939 Rev 1

2

Functional description

The STV7623 includes all the logic and power circuits necessary to drive the thin-film

transistor (TFT) of an active matrix display backplane. A low-voltage logic block manages

data information, and a high-voltage block converts the low-voltage information stored in the

logic block into high-voltage signals applied to the display gate lines.

2.1

Device operation

In the condition of DIR=L, the STV1 start pulse input is sensed at the rising edge of CLK and

stored in the first stage of shift register, which causes the first scan signal is outputted from

the OUT1 output pin. While stored data is transferred to the next stage of the shift register at

the rising edge of the CLK signal, new data of STV1 is sensed and stored simultaneously.

The output pin (OUT1 to OUT480) supplies VP or VN voltage to the gate lines depending on

the data stored in the shift register. For normal operation, a VP voltage is outputted one by

one like a shift token from OUT1 to OUT480, in sync with CLK pulse.

STV2 goes up to high level at the 400/480th falling edge of CLK and goes down to low level

at the 401/481th falling edge of CLK. This STV2 is connected to the next driver IC STV1

signal to cascade (daisy chain) them.

When STV2 is an output, the signal is activated for 1/2 clock later.

When the chip is configured in 400 output mode, only the first 400 bits entering the shift

register are used, the remaining 80 outputs are removed from the shift register.

Figure 3.

Example of input/output timing DIR = H

1

2

3

4

5

6

7

479

480

481

482

CLK

STV1

BLANK

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT480

STV2

Example of input/output timing (DIR=0)