910GL datasheet(99/426 Pages) INTEL

99 / 426 page

MCHBAR Registers

Datasheet

5.1.5

C0DRA0—Channel A DRAM Rank 0,1 Attribute

MMIO Range:

MCHBAR

Address Offset:

108h

Default Value:

00h

Access:

R/W

Size:

8 bits

The DRAM Rank Attribute Registers define the page sizes to be used when accessing different

ranks. These registers should be left with their default value (all zeros) for any rank that is

unpopulated, as determined by the corresponding CxDRB registers. Each byte of information in

the CxDRA registers describes the page size of a pair of ranks.

Channel and Rank Map:

Channel A Rank 0, 1:

108h

Channel A Rank 2, 3:

109h

Channel B Rank 0, 1:

188h

Channel B Rank 2, 3:

189h

Bit

Access &

Default

Description

Reserved

6:4

R/W

000b

Channel A DRAM odd Rank Attribute: This 3 bit field defines the page size of

the corresponding rank.

000 = Unpopulated

001 = Reserved

010 = 4 KB

011 = 8 KB

100 = 16 KB

Others = Reserved

Reserved

2:0

R/W

000b

Channel A DRAM even Rank Attribute: This 3 bit field defines the page size of

the corresponding rank.

000 = Unpopulated

001 = Reserved

010 = 4 KB

011 = 8 KB

100 = 16 KB

Others = Reserved

5.1.6

C0DRA2—Channel A DRAM Rank 2,3 Attribute

MMIO Range:

MCHBAR

Address Offset:

109h

Default Value:

00h

Access:

R/W

Size:

8 bits

The operation of this register is detailed in the description for register C0DRA0.

910GL Fiches technique(PDF) 99 Page - Intel Corporation

910GL Fiches technique(HTML) 99 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL