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910GL Fiches technique(PDF) 75 Page - Intel Corporation

No de pièce 910GL
Description  Express Chipset
PDF  426 Pages
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Fabricant  INTEL [Intel Corporation]
Site Internet  http://www.intel.com
Logo INTEL - Intel Corporation

910GL Fiches technique(HTML) 75 Page - Intel Corporation

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Host Bridge/DRAM Controller Registers (D0:F0)
R
Datasheet
75
4.1.13
MCHBAR—(G)MCH Memory Mapped Register Range Base
Address (D0:F0)
PCI Device:
0
Address Offset:
44h
Default Value:
00000000h
Access:
R/W
Size:
32 bits
This is the base address for the (G)MCH memory-mapped configuration space. There is no
physical memory within this 16-KB window that can be addressed. The 16 KB reserved by this
register does not alias to any PCI 2.3 compliant memory mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0,
offset 54h, bit 28]
Bit
Access &
Default
Description
31:14
R/W
00000h
(G)MCH Memory Mapped Base Address: This field corresponds to bits 31:14 of
the base address (G)MCH memory-mapped configuration space.
BIOS will program this register resulting in a base address for a 16-KB block of
contiguous memory address space. This register ensures that a naturally aligned
16-KB space is allocated within total addressable memory space of 4 GB.
System software uses this base address to program the (G)MCH Memory-
mapped register set.
13:0
Reserved



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