KB8821 datasheet(4/21 Pages) SAMSUNG

4 / 21 page

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

KB8821/22/23

99-06-15

PIN DESCRIPTION

Pin No

Symbol

I / O

Description

VDD1

Power supply voltage input for the RF PLL part. VDD1 must equal VDD2. In

order to reject supply noise, bypass capacitors must be placed as close as

possible to this pin and be connected directly to the ground plane.

Vp1

Power supply voltage input for RF charge pump(

≥ VDD1).

CPoRF

Internal RF charge pump output for connection to an external loop filter whose

filtered output drives an external VCO.

GND

Ground for RF digital blocks.

finRF

RF prescaler input. The signal comes from the external VCO.

finRF

The complementary input of the RF prescaler. A bypass capacitor must be

placed as close as possible to this pin and be connected directly to the ground

plane. The bypass capacitor is optional with some loss of sensitivity.

GND

Ground for RF analog blocks.

OSCin

Reference counter input. TCXO is connected via a coupling capacitor.

GND

Ground for IF digital blocks.

foLD

Multiplexed output of the RF/IF programmable counters, the reference

counters, the lock detect signals and the shift registers. The output level is

CMOS level. (see fout Programmable Truth Table)

CLOCK

CMOS clock input. Serial data for the various counters is transfered into the

22-bit shift register on the rising edge of the clock signal.

DATA

Binary serial data input. The MSB of CMOS input data is entered first. The

control bits are on the last two bits. CMOS input.

Load enable CMOS input. When LE becomes high, the data in the shift

GND

Ground for IF analog blocks.

finIF

The complementary input of the IF prescaler. A bypass capacitor must be

placed as close as possible to this pin and be connected directly to the ground

plane. The bypass capacitor is optional with some loss of sensitivity.

finIF

IF prescaler input. The signal comes from the external VCO.

GND

Ground for IF digital blocks.

CPoIF

Internal IF charge pump output for connection to an external loop filter whose

filtered output drives an external VCO.

Vp2

Power supply voltage input for IF charge pump(

≥ VDD2)

VDD2

Power supply voltage input for the IF PLL part. VDD1 must equal VDD2. In

order to reject supply noise, bypass capacitors must be placed as close as

possible to this pin and be connected directly to the ground plane.

KB8821 Fiches technique(PDF) 4 Page - Samsung semiconductor

KB8821 Fiches technique(HTML) 4 Page - Samsung semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Fiches technique Télécharger

Lien URL