P89LPC9331FDH datasheet(32/93 Pages) NXP

32 / 93 page

P89LPC9331_9341_9351_9361_3

Product data sheet

Rev. 03 — 2 June 2009

32 of 93

NXP Semiconductors

P89LPC9331/9341/9351/9361

8-bit microcontroller with accelerated two-clock 80C51 core

7.10 CCLK wake-up delay

The P89LPC9331/9341/9351/9361 has an internal wake-up timer that delays the clock

until it stabilizes depending on the clock source used. If the clock source is any of the

three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK

cycles plus 60

µsto100 µs. If the clock source is the internal RC oscillator, the delay is

200

µs to 300 µs. If the clock source is watchdog oscillator or external clock, the delay is

32 OSCCLK cycles.

7.11 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

7.12 Low power select

The P89LPC9331/9341/9351/9361 is designed to run at 18 MHz (CCLK) maximum.

However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1

to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest

performance access. This bit can then be set in software if CCLK is running at 8 MHz or

slower.

Fig 7.

Block diagram of oscillator control

÷2

002aad559

RTC

ADC1

ADC0

CPU

WDT

DIVM

CCLK

UART

OSCCLK

I2C-BUS

PCLK

TIMER 0 AND

TIMER 1

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

XTAL1

XTAL2

RC OSCILLATOR

WITH CLOCK DOUBLER

WATCHDOG

OSCILLATOR

(7.3728 MHz/14.7456 MHz

± 1 %)

PCLK

RCCLK

SPI

CCU

(P89LPC9351/9361)

× PLL

(400 kHz

± 5 %)

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