LPC1114FA44SLASH301 datasheet(46/59 Pages) NXP

46 / 59 page

LPC1111_12_13_14_1

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 01 — 16 April 2010

46 of 59

NXP Semiconductors

LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

[1]

Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),

and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).

[2]

Tamb = −40 °C to 85 °C.

[3]

Tcy(clk) = 12 × Tcy(PCLK).

[4]

Tamb = 25 °C; for normal voltage supply range: VDD = 3.3 V.

tDH

data hold time

in SPI mode

[3][4]

× T

cy(PCLK) + 4

tv(Q)

data output valid time in SPI mode

[3][4]

× T

cy(PCLK) + 11

th(Q)

data output hold time in SPI mode

[3][4]

× T

cy(PCLK) + 5

Table 16.

Dynamic characteristics of SPI pins in SPI mode

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 22. SPI master timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk)

tclk(H)

tclk(L)

tDS

tDH

tv(Q)

DATA VALID

th(Q)

SCK (CPOL = 1)

DATA VALID

MOSI

MISO

tDS

tDH

DATA VALID

th(Q)

DATA VALID

tv(Q)

CPHA = 1

CPHA = 0

002aae829

LPC1114FA44/301 Fiches technique(PDF) 46 Page - NXP Semiconductors

LPC1114FA44/301 Fiches technique(HTML) 46 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Fiches technique Télécharger

Lien URL