AT697F datasheet(130/155 Pages) ATMEL

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130

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

AC Characteristics The AT697 processor implements a single event transient protection mechanism. The influence

of this protection is reflected by the timing figures presented in the following tables.

The following tables show the timing figures for the skew condition natural and maximum.

Natural Skew

Test Conditions

•

Natural Skew

•

Temperature range : -55°C to 125°C

•

Voltage range :

–

I/O: 3.3V +/- 0.30V

–

Core: 1.8V +/- 0.15V

•

Output load : 30pF

Table 126. AC Characteristics - Natural Skew

Parameter

Min

(ns)

Max

(ns)

Comment

Reference edge

(‘+’ for rising edge)

CLK Period with PLL disable

t1_p

CLK Period with PLL enable

4.5

CLK Low and High pulse width - PLL disabled

t2_p

CLK Low and High pulse width - PLL enabled

SDCLK Period

3.5

SDCLK output delay - PLL disabled

CLK

1.107

PLL setup time

1*t3

Reset Pulse Width

t10

1.5

A[27:0] output delay

SDCLK +

t11

1.5

D[31:0] and CB[7:0] output delay

SDCLK +

t12

D[31:0] and CB[7:0] setup time

SDCLK +

t13

D[31:0] and CB[7:0] hold time during load/fetch

SDCLK +

t14

D[31:0] and CB[7:0] hold time during write

SDCLK +

t15

1.5

OE*, READ and WRITE* output delay

SDCLK +

t16

ROMS*[1:0] output delay

SDCLK +

t17

1.5

RAMS*[4:0], RAMOE*[4:0] and RWE*[3:0] output delay

SDCLK +

t18

1.5

IOS* output delay

SDCLK +

t19

BRDY* setup time

SDCLK +

t20

BRDY* hold time

SDCLK +

t21

2.5

8.5

SDCAS* output delay

SDCLK +

t22

2.5

8.5

SDCS*[1:0], SDRAS*, SDWE* and SDDQM*[3:0] output delay

SDCLK +

t23

BEXC* setup time

SDCLK +

t24

BEXC* hold time

SDCLK +

t25

2.5

PIO[15:0] output delay

SDCLK +

t26

PIO[15:0] setup time

SDCLK +

AT697F Fiches technique(PDF) 130 Page - ATMEL Corporation

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