ST7263BHX datasheet(75/186 Pages) STMICROELECTRONICS

75 / 186 page

ST7263Bxx

On-chip peripherals

Doc ID 7516 Rev 8

75/186

Control/status register (CSR)

Reset value: xxxx x0xx (xxh)

Table 24.

Clock Control bits

Timer clock

CC1

CC0

fCPU / 4

fCPU / 2

fCPU / 8

External Clock (where available)

765

ICF1

OCF1

TOF

ICF2

OCF2

TIMD

Read only

Read/write

7 ICF1 input Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin or the counter has reached the

OC2R value in PWM mode. To clear this bit, first read the SR register, then read or

write the low byte of the IC1R (IC1LR) register.

6 OCF1 output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has matched the content of the OC1R

the OC1R (OC1LR) register.

5 TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1:The free running counter rolled over from FFFFh to 0000h. To clear this bit, first

read the SR register, then read or write the low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

4 ICF2 input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the

SR register, then read or write the low byte of the IC2R (IC2LR) register.

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