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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ST7263BHx Fiches technique(PDF) 53 Page - STMicroelectronics |
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ST7263BHx Fiches technique(HTML) 53 Page - STMicroelectronics |
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53 / 186 page  ST7263Bxx Miscellaneous register Doc ID 7516 Rev 8 53/186 10 Miscellaneous register Miscellaneous register (MISCR) Address: 0009h Reset value: 0000 0000 (00h) 7 0 -- -- - SMS USBOE MCO Read/write [7:3] Reserved 2 SMS Slow mode Select. This bit is set by software and only cleared by hardware after a reset. If this bit is set, it enables the use of an internal divide-by-2 clock divider (refer to Figure 18 on page 36). The SMS bit has no effect on the USB frequency. 0: Divide-by-2 disabled and CPU clock frequency is standard 1: Divide-by-2 enabled and CPU clock frequency is halved. 1 USBOE USB enable. If this bit is set, the port PC2 (PB1 on SO24) outputs the USB output enable signal (at “1” when the ST7 USB is transmitting data). Unused bits 7-4 are set. 0 MCO Main Clock Out selection This bit enables the MCO alternate function on the PA0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU on I/O port) |
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