TMS320VC33 datasheet(36/57 Pages) TI

36 / 57 page

TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

XF0 and XF1 timing when executing SIGI

The following tables define the timing parameters for the XF0 and XF1 pins during execution of SIGI.

timing requirements for XF0 and XF1 when executing SIGI (see Figure 24)

VC33-120

VC33-150

UNIT

MIN

MAX

MIN

MAX

UNIT

tsu(XF1-H1L)

Setup time, XF1 before H1 low

th(H1L-XF1)

Hold time, XF1 after H1 low

switching characteristics over recommended operating conditions for XF0 and XF1 when executing

SIGI (see Figure 24)

PARAMETER

VC33-120

VC33-150

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

td(H3H-XF0L)

Delay time, H3 high to XF0 low

td(H3H-XF0H)

Delay time, H3 high to XF0 high

Fetch

SIGI

Decode

Read

Execute

XF0

XF1

tsu(XF1-H1L)

th(H1L-XF1)

td(H3H-XF0L)

td(H3H-XF0H)

Figure 24. Timing for XF0 and XF1 When Executing SIGI

TMS320VC33 Fiches technique(PDF) 36 Page - Texas Instruments

TMS320VC33 Fiches technique(HTML) 36 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Fiches technique Télécharger

Lien URL