CDC921

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS

WITH 3-STATE OUTPUTS

SCAS623 –MAY 27, 1999

2

POST OFFICE BOX 655303

description (continued)

The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding

setting for SEL133/100 control input. The PCI bus frequency is fixed to 33 MHz.

Since the CDC921 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL.

This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an

external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts.

Function Tables

SELECT FUNCTIONS

INPUTS

OUTPUTS

SEL133/

100

SEL1

SEL0

CPU

CPU_DIV2

3V66

PCI

48MHz

REF

APIC

FUNCTION

L

L

L

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

3-state

L

L

H

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Reserved

L

H

L

100 MHz

50 MHz

66 MHz

33 MHz

Hi-Z

14.318 MHz

16.67 MHz

48-MHz PLL off

L

H

H

100 MHz

50 MHz

66 MHz

33 MHz

48 MHz

14.318 MHz

16.67 MHz

48-MHz PLL on

H

L

L

TCLK/2

TCLK/4

TCLK/4

TCLK/8

TCLK/2

TCLK

TCLK/16

Test

H

L

H

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Reserved

H

H

L

133 MHz

66 MHz

66 MHz

33 MHz

Hi-Z

14.318 MHz

16.67 MHz

48-MHz PLL off

H

H

H

133 MHz

66 MHz

66 MHz

33 MHz

48 MHz

14.318 MHz

16.67 MHz

48-MHz PLL on

ENABLE FUNCTIONS

INPUTS

OUTPUTS

INTERNAL

PWR_DWN

CPU

CPU_DIV2

APIC

3V66

PCI

REF,

48MHz

CRYSTAL

VCOs

L

L

L

L

L

L

L

Off

Off

H

On

On

On

On

On

On

On

On

OUTPUT BUFFER SPECIFICATIONS

BUFFER NAME

VDD RANGE

(V)

IMPEDANCE

(

Ω)

BUFFER TYPE

CPU, CPU_DIV2, APIC

2.375 – 2.625

13.5 – 45

TYPE 1

48MHz, REF

3.135 – 3.465

20 – 60

TYPE 3

PCI, 3V66

3.135 – 3.465

12 – 55

TYPE 5