CDC921

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS

WITH 3-STATE OUTPUTS

SCAS623 –MAY 27, 1999

14

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

tr

3 V

0 V

VIH_REF

VT_REF

VIL_REF

VT_REF

VT_REF

tPLH

tPHL

tf

tw_high

tw_low

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

RL = 500 Ω

LOAD CIRCUIT for tpd and tsk

From Output

Under Test

CL

(see Note A)

RL = 500 Ω

S1

VO_REF

OPEN

GND

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

VO_REF

GND

TEST

S1

tw

Input

3 V

0 V

VIH_REF

VT_REF

VIL_REF

From Output

Under Test

Test

Point

CL

(see Note A)

LOAD CIRCUIT FOR tr and tf

VOLTAGE WAVEFORMS

0 V

Output

Waveform 2

S1 at GND

(see Note B)

VOLTAGE WAVEFORMS

VOH

VOL

VDD

VT_REF

VT_REF

VT_REF

tPZL

tPLZ

tPHZ

tPZH

VT_REF

VOH – 0.3 V

VOL + 0.3 V

≈3 V

≈0 V

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Enable

(high-level

enabling)

NOTES: A. CL includes probe and jig capacitance. CL = 20 pF (CPUx, APIC, 48MHz, REF), CL = 30 pF (PCIx)

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

v 14.318 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,

tf ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

PARAMETER

3.3-V INTERFACE

2.5-V INTERFACE

UNIT

VIH_REF

High-level reference voltage

2.4

2

V

VIL_REF

Low-level reference voltage

0.4

0.4

V

VT_REF

Input Threshold reference voltage

1.5

1.25

V

VO_REF

Off-state reference voltage

6

4.6

V

Figure 3. Load Circuit and Voltage Waveforms