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CDC921 Fiches technique(PDF) 12 Page - Texas Instruments |
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CDC921 Fiches technique(HTML) 12 Page - Texas Instruments |
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12 / 17 page ![]() CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS623 –MAY 27, 1999 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued) 48MHz PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT ten1 Output enable time SEL133/100 48MHz f(48MHz) = 48 MHz 6 10 ns tdis1 Output disable time SEL133/100 48MHz f(48MHz) = 48 MHz 8 10 ns tc 48MHz clock period† f(48MHz) = 48 MHz 20.5 20.83 21.1 ns Cycle to cycle jitter f(CPU) = 100 or 133 MHz 500 ps Duty cycle f(48MHz) = 48 MHz 45 55 % tsk(p) 48MHz pulse skew 48MHz 48MHz f(48MHz) = 48 MHz 3 ns tw1 Pulse duration width, high f(48MHz) = 48 MHz 7.8 ns tw2 Pulse duration width, low f(48MHz) = 48 MHz 7.8 ns tr Rise time VO = 0.4 V to 2 V 1 2.1 2.8 ns tf Fall time VO = 0.4 V to 2 V 1 1.9 2.8 ns † The average over any 1- µs period of time is greater than the minimum specified period. REF PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT ten1 Output enable time SEL133/100 REFx f(REF) = 14.318 MHz 6 10 ns tdis1 Output disable time SEL133/100 REFx f(REF) = 14.318 MHz 8 10 ns tc REF clock period† f(REF) = 14.318 MHz 69.84 ns Cycle to cycle jitter f(CPU) = 100 or 133 MHz 700 ps Duty cycle f(REF) = 14.318 MHz 45 55 % tsk(o) REF bus skew REFx REFx f(REF) = 14.318 MHz 150 250 ps tsk(p) REF pulse skew REFn REFn f(REF) = 14.318 MHz 2 ns tw1 Pulse duration width, high f(REF) = 14.318 MHz 26.2 32.7 ns tw2 Pulse duration width, low f(REF) = 14.318 MHz 26.2 31.2 ns tr Rise time VO = 0.4 V to 2 V 1 2 2.8 ns tf Fall time VO = 0.4 V to 2 V 1 1.9 2.8 ns † The average over any 1- µs period of time is greater than the minimum specified period. |
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