LT6556IGN datasheet(11/16 Pages) LINER

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LT6556

6556f

APPLICATIO S I FOR ATIO

enabled output. However, since the disabled LT6556 and its

traces have around 6pF of capacitance, it may be desirable

to resistively isolate the outputs of each channel to maintain

ﬂat frequency response as shown in the graph labeled

“Maximum Capacitive Load vs Output Series Resistor” in

the Typical Performance Characteristics section.

ESD Protection

The LT6556 has reverse-biased ESD protection diodes on all

pins. If any pins are forced a diode drop above the positive

supply or a diode drop below the negative supply, large

currents may ﬂow through these diodes. If the current is

kept below 10mA, no damage to the devices will occur.

TYPICAL APPLICATIO

RGB Multiplexer Demo Board

The DC892A Demo Board illustrates optimal routing,

bypassing and termination using the LT6556 as an

RGB video multiplexer. The schematic is shown in Figure 6.

All inputs and outputs are routed to have a characteristic

impedance of 75Ω and 75Ω input shunt and output series

terminations are connected as close to the part as pos-

sible. The board is fabricated with four layers with internal

ground and power planes.

While the 75Ω back termination resistors at the outputs

of the LT6556 minimize signal reﬂections in the output

traces and isolate the part from any capacitive loading in

those traces, they also contribute to gain error if the out-

put is not terminated with high impedance. For example,

if the output is terminated with a 1k load, the 75Ω back

termination will cause a 7% gain error. Decreasing the

value of the back termination resistors will decrease the

signal attenuation but may compromise the AC response.

However, connecting the LT6556 output pins to the output

traces on the DC892A board without some series resistance

is not recommended; 10Ω to 20Ω is generally sufﬁcient.

Figures 7 and 8 show the top and bottom side board layout

and placement.

Figure 6. Demo Board Schematic

IN1A

IN2A

IN3A

IN1B

IN2B

IN3B

IN1B

AGND1

IN3A

VREF

IN2A

DGND

IN1A

AGND2

V+

OUT2

V–

OUT1

IN3B

AGND3

IN2B

V–

V+

V–

OUT3

V+

SEL

V+

U1 LT6556CUF

EXT

GND

JP5

VREF

JP12

BNC × 6

DGND

Z = 75

JP13

JP14

JP5

JP6

JP7

BANANA JACK

FLOAT

AGND

JP2

DGND

EXT

ENABLE

JP1

CONTROL

VCC

SEL A/B

DGND

JP4

SEL

20k

50Ω BNC

5432

R10

75Ω

R11

75Ω

R12

75Ω

DUAL

NOTE:

470pF BYPASS CAPACITORS LOCATED

AS CLOSE TO PINS AS POSSIBLE

SINGLE

AGND

JP3

SUPPLY

SEL A/B

DGND

VREF

AGND

50Ω

OPT

Z = 50

OUT1

Z = 75

75Ω

Z = 75

J10

J11

BANANA JACK

VEE

6556 F06

OUT2

OUT3

VEE

–3.3V TO –5V

4700pF

C10

4700pF

0.33μF

10V

470pF

10μF

16V

1206

10μF

16V

1206

BANANA JACK

VCC

3.3V TO 5V

4700pF

470pF

0.33μF

10V

BNC × 3

5432

50Ω

OPT

50Ω BNC

SEL A/B

V–

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