LT6556IGN datasheet(8/16 Pages) LINER

8 / 16 page

LT6556

6556f

APPLICATIO S I FOR ATIO

Power Supplies

The LT6556 is optimized for ±5V supplies but can be op-

erated on as little as ±2.25V or a single 4.5V supply and

as much as ±6V or a single 12V supply. Internally, each

supply is independent to improve channel isolation. Do

not leave any supply pins disconnected or the part may

not function correctly!

Enable/Shutdown

The LT6556 has a shutdown mode controlled by the

⎯E⎯N

pin and referenced to the DGND pin. If the ampliﬁer will be

enabled at all times, the

⎯E⎯N pin can be connected directly

to DGND. If the enable function is desired, either driving

the pin above 2V or allowing the internal 46k pull-up

resistor to pull the

⎯E⎯N pin to the top rail will disable the

ampliﬁer. When disabled, the output will become very

high impedance. Supply current into the ampliﬁer in the

disabled state will be:

–

– –

It is important that the following constraints on the DGND,

⎯E⎯N and SEL pins are always followed:

V+ – VDGND ≥ 4.5V

-0.5V ≤ V⎯E⎯N – VDGND ≤ 5.5V

VSEL – VDGND ≤ 8V

In dual supply cases where V+ is less than 4.5V, DGND

should be connected to a potential below ground, such as

V–. Since the

⎯E⎯N and SEL pins are referenced to DGND, they

may need to be pulled below ground in those cases. However,

in order to protect the internal enable circuitry, the

⎯E⎯N pin

should not be forced more than 0.5V below DGND.

In single supply applications above 5.5V, an additional

resistor may be needed from the

⎯E⎯N pin to DGND if the

pin is ever allowed to ﬂoat. For example, on a 12V single

supply, a 33k resistor would protect the pin from ﬂoating

too high while still allowing the internal pull-up resistor

to disable the part.

On dual ±2.25V supplies, connecting the DGND pin to V– is

the only way of ensuring that V+ – VDGND ≥ 4.5V.

The enable/disable times of the LT6556 are fast when

driven with a logic input. Turn on (from 50%

⎯E⎯N input to

50% output) typically occurs in less than 50ns. Turn off

is slower, but is typically below 500ns.

Channel Select

The SEL pin uses the same internal threshold as the

⎯E⎯N

pin and is also referenced to DGND. When the pin is logic

low, the channel A inputs are passed to the output. When

the pin is logic high, the channel B inputs are passed to

the output. The pin should not be ﬂoated but can be tied

to DGND to force the outputs to always be channel A or

to V+ (when less than 8V) to force the outputs to always

be channel B.

Truth Table

SEL

⎯A/B

⎯E⎯N

OUT

IN A

IN B

OFF

Input Considerations

The LT6556 uses input clamps referenced to the VREF pin

to prevent damage to the input stage on the unselected

channel. Three transistors in series limit the input voltage to

within three diode drops (±) from VREF. VREF is nominally

set to half of the sum of the supplies by the 40k resistors.

A simpliﬁed schematic is shown in Figure 1.

VREF

40k

6556 F01

V+

V–

Figure 1. Simpliﬁed Schematic of VREF Pin and Input Clamping

LT6556IGN Fiches technique(PDF) 8 Page - Linear Technology

LT6556IGN Fiches technique(HTML) 8 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Fiches technique Télécharger

Lien URL