CS42324 datasheet(49/71 Pages) CIRRUS

49 / 71 page

DS721A6

CS42324

6.3.6

Tri-State Serial Port 2

When enabled, and the device is configured as a master, then SCLK2 and LRCK2 of Serial Port 2 (SP2)

will be placed in a high-impedance output state. If Serial Port 2 is configured as a slave, SCLK2 and

LRCK2 will remain as inputs. SDIN1 and SDIN2 are always configured as inputs.

6.4

Serial Port 1 Control (Address 03h)

6.4.1

Serial Port 1 Master/Slave Select

This bit configures Serial Port 1 to operate as either a clock master or clock slave.

6.4.2

Serial Port 1 Speed Mode

In Master Mode this bit configures the speed mode of Serial Port 1.

6.4.3

MCLK1 Divider

These bits configure the internal MCLK1 dividers.

6.4.4

Serial Port 1 MCLK source

This bit selects which MCLK pin provides the clock for deriving Master Mode sub-clocks for Serial Port 1.

TRI-SP2

SCLK2 and LRCK2 State

SCLK2 and LRCK2 operate as inputs if Serial Port 2 is configured as a slave; SCLK2 and LRCK2

operate as outputs if Serial Port 2 is configured as a master

SCLK2 and LRCK2 operate as inputs if Serial Port 2 is configured as a slave; SCLK2 and LRCK2

become high-impedance outputs if Serial Port 2 is configured as a master

432

SP1_M/S

Reserved

SP1_SPEED

MCLK1

FREQ1

MCLK1

FREQ0

Reserved

SP1_MCLK

SP1_M/S

Serial Port 1 Master/Slave Select

Slave Mode

Master Mode

SP1_SPEED

Serial Port 1 Speed Mode

Single-Speed Mode (SSM)

Double-Speed Mode (DSM)

MCLK1

FREQ[1:0]

MCLK Divider

÷1

÷1.5

÷2

÷3

SP1_MCLK

Serial Port 1 MCLK source

MCLK1

1MCLK2

CS42324 Fiches technique(PDF) 49 Page - Cirrus Logic

CS42324 Fiches technique(HTML) 49 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

Fiches technique Télécharger

Lien URL