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HD6432351 Fiches technique(PDF) 157 Page - Renesas Technology Corp |
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HD6432351 Fiches technique(HTML) 157 Page - Renesas Technology Corp |
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157 / 1025 page ![]() Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 123 of 988 REJ09B0330-0300 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. Area decoder Bus controller ABWCR ASTCR BCRH BCRL Internal address bus CS0 to CS7 External bus control signals BREQ BACK BREQO Internal control signals Wait controller WCRH WCRL Bus mode signal DRAM controller RTCNT RTCOR DRAMCR MCR Bus arbiter CPU bus request signal DTC bus request signal DMAC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal External DRAM signals WAIT Figure 6.1 Block Diagram of Bus Controller |
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