HD6432351 datasheet(11/1025 Pages) RENESAS

11 / 1025 page

Rev. 3.00 Sep 15, 2006 page xi of xxxiv

Item

Page

Revision (See Manual for Details)

14.2.2 Serial Status

617

Bits 3 to 0

Bit 2 table amended

Bit 2

TEND

Description

Indicates data transmission in progress

[Clearing conditions]

(Initial value)

When 0 is written to TDRE after reading TDRE = 1

When the DMAC or DTC is activated by a TXI interrupt and write data to TDR

Indicates that data transmission in finished

[Setting conditions]

Upon reset, and in standby mode or module stop mode

When the TE bit in SCR is 0 and the ERS bit is also 0

When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a

1-byte serial character when GM = 0

When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a

1-byte serial character when GM = 1

14.3.2 Pin Connections

Figure 14.2 Schematic

Diagram of Smart Card

Interface Pin

Connections

621

Figure 14.2 amended

H8S/2350 Group

14.3.4 Register

Settings

625

Smart Card Mode Register (SCMR) Setting

Inverse convention (SDIR = SINV = O/

E = 0)

Description amended

... With the H8S/2350 Group, invention specified by the SNIV

bit ...

14.3.6 Data Transfer

Operations

Figure 14.6 TEND Flag

Generation Timing in

Transmission Operation

631

Figure 14.6 amended

Guard

time

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