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HD6432351 Fiches technique(PDF) 121 Page - Renesas Technology Corp

No de pièce HD6432351
Description  16-Bit Single-Chip Microcomputer
PDF  1025 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432351 Fiches technique(HTML) 121 Page - Renesas Technology Corp

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Section 4 Exception Handling
Rev. 3.00 Sep 15, 2006 page 87 of 988
REJ09B0330-0300
4.5
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.5 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.5
Status of CCR and EXR after Trap Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
I2 to I0
T
0
1
—
—
—
2
1
—
—
0
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.



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