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HD6432351 Fiches technique(PDF) 474 Page - Renesas Technology Corp |
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HD6432351 Fiches technique(HTML) 474 Page - Renesas Technology Corp |
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474 / 1025 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Sep 15, 2006 page 440 of 988 REJ09B0330-0300 10.2.4 Timer Interrupt Enable Register (TIER) 7 TTGE 0 R/W 6 — 1 — 5 — 0 — 4 TCIEV 0 R/W 3 TGIED 0 R/W 0 TGIEA 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W Bit Initial value R/W : : : Channel 0: TIER0 Channel 3: TIER3 7 TTGE 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 — 0 TGIEA 0 R/W 2 — 0 — 1 TGIEB 0 R/W Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 Bit Initial value R/W : : : The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset, and in hardware standby mode. |
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