HD404612FS datasheet(13/91 Pages) RENESAS

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HD404618 Series

Bit 3

Bit 2

Bit 1

Bit 0

IM0

(IM of

INT )

IF0

(IF of

INT )

RSP

(Reset SP bit)

(Interrupt enable flag)

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of

INT )

IF1

(IF of

INT )

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMTB

(IM of timer B)

IFTB

(IF of timer B)

Not used

IMS

(IM of serial)

IFS

(IF of serial)

$000

$001

$002

$003

DTON

Direct transfer on flag

TGSP

(Tone generator

speed flag)

WDON

(Watchdog on flag)

LSON

(Low speed on flag)

Not Used

$020

$021

$023

IF: Interrupt request flag

IM: Interrupt mask

IE: Interrupt enable flag

SP: Stack pointer

Note:

Bits in the interrupt control bits area and register flag area are set by the SEM or SEMD

instruction, reset by the REM or REMD instruction, and tested by the TM or TMD instruction.

Other instructions have no effect.

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

RSP

WDON

TGSP

DTON

SEM/SEMD

REM/REMD

TM/TMD

Not executed

Allowed

Not executed

Allowed

Inhibited

Allowed

Not executed

Inhibited

Allowed

Inhibited

Not executed in active mode

Allowed

Used in subactive mode

Note: WDON is always reset in active mode.

DTON is always reset in active mode.

If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,

the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

HD404612FS Fiches technique(PDF) 13 Page - Renesas Technology Corp

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