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TS4601B Fiches technique(PDF) 18 Page - STMicroelectronics

No de pièce TS4601B
Description  High performance stereo headphone amplifier with capacitorless outputs and I2C bus interface
PDF  28 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

TS4601B Fiches technique(HTML) 18 Page - STMicroelectronics

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Application information
TS4601B
18/28
To write in the control registers:
In order to write data into the TS4601B, after the “start” message, the MCU must:
●
send byte with the I²C 7-bit slave address and with a low level for the R/W bit
●
send the data (control register setting)
All bytes are sent with MSB first. The transfer of written data ends with a “stop” message.
When transmitting several data, the data can be written with no need to repeat the “start”
message and addressing byte with the slave address.
When writing several bytes, the data is transmitted as follows:
●
CR1 CR2 CR2 CR2... this is an advantage for a fast increase/decrease of the volume
control.
Figure 50.
I²C write operations
To read from the control registers:
In order to read data from the TS4601B, after the “start” message, the MCU must:
●
send byte with the I²C 7-bit slave address and with a high level for the R/W bit
●
receive the data (control register value)
All bytes are read with MSB first. The transfer of read data ends with the “stop” message.
When transmitting several data, the data can be read with no need to repeat the “start”
message and the byte with the slave address. In this case, the value of the control register is
read repeatedly, CR0, CR1, CR2, CR3, CR4, CR0, CR1 etc.
Table 9.
Control registers summary
Description
D7
D6
D5
D4
D3
D2
D1
D0
CR0
SC_L
SC_R
T_SH
000
00
CR1 - modes
Output modes
0
0
0
0
0
CR2 - volume control
Mute_L
Mute_R
Volume control
CR3
000
000
00
CR4 - identification
010
000
10
SDA
S
11
0
0
0
0
A
00
D7
D7
D0
D1
A
P
Start condition
SLAVE ADDRESS
CONTROL REGISTERS
R/W
Acknowledge
from Slave
Acknowledge
from Slave
Stop
condition
D6
D6
D1 D0
D7 D6
D1 D0
CR1
CR2
CR2
A
A
SDA
S
11
0
0
0
0
A
00
D7
D7
D0
D1
A
P
Start condition
SLAVE ADDRESS
CONTROL REGISTERS
R/W
R/W
Acknowledge
from Slave
Acknowledge
from Slave
Stop
condition
D6
D6
D1 D0
D7 D6
D1 D0
CR1
CR2
CR2
A
A



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