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EVAL-ADE7569F16EB Fiches technique(PDF) 96 Page - Analog Devices

No de pièce EVAL-ADE7569F16EB
Description  Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
PDF  136 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

EVAL-ADE7569F16EB Fiches technique(HTML) 96 Page - Analog Devices

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ADE7566/ADE7569
Preliminary Technical Data
Rev. PrA | Page 96 of 136
The program counter (PC) is held on the instruction where the
ECON register is written to until the flash memory controller is
done performing the requested operation. Then, the PC
increments to continue with the next instruction.
Any interrupt requests that occur while the flash controller is
performing an operation are not handled until the flash operation
is complete. All peripherals, such as timers and counters, continue
to operate as configured throughout the flash memory access.
Table 88. Flash Control SFR (ECON, 0xB9)
Bit No.
Mnemonic
Value
Description
7 to 0
ECON
1
Write Byte. The value in EDATA is written to the flash memory at the page address given by EADRH and
EADRL. Note that the byte being addressed must be pre-erased.
2
Erase Page. A 512-byte page of flash memory address is erased. The page is selected by the address in
EADRH/EADRL. Any address in the page can be written to EADRH/EADRL to select it for erasure.
3
Erase All. All 16 kB of the flash memory are erased. Note that this command is used during serial and
parallel download modes but should not be executed by user code.
4
Read Byte. The byte in the flash memory addressed by EADRH/EADRL is read into EDATA.
5
Erase Page and Write Byte. The page that holds the byte addressed by EADRH/EADRL is erased. Data in
EDATA is then written to the byte of flash memory addressed by EADRH/EADRL.
8
Protect Code (see the Protecting the Flash section).
Table 89. Flash Key SFR (FLSHKY, 0xBA)
Bit No.
Mnemonic
Default
Description
7 to 0
FLSHKY
0xFF
The content of this SFR is compared to the flash key, 0x3B. If the two values match, the next ECON
operation is allowed (see the Protecting the Flash section).
Table 90. Flash Protection Key SFR (PROTKY, 0xBB)
Bit No.
Mnemonic
Default
Description
7 to 0
PROTKY
0xFF
The content of this SFR is compared to the flash memory location at address 0x3FFA. If the two values match,
the update of the write/erase and read protection set up is allowed (see the Protecting the Flash section).
If the protection key in the flash is 0xFF, the PROTKY SFR value is not used for comparison. This SFR is also
used to write the protection key in the flash. This is done by writing the desired value in PROTKY and by
writing 0x08 in the ECON SFR. This operation can only be done once.
Table 91. Flash Data SFR (EDATA, 0xBC)
Bit No.
Mnemonic
Default
Description
7 to 0
EDATA
0
Flash Pointer Data.
Table 92. Flash Write/Erase Protection 0 SFR (PROTB0, 0xBD)
Bit No.
Mnemonic
Default
Description
7 to 0
PROTB0
0xFF
This SFR is used to write the write/erase protection bits for Page 0 to Page 7 of the flash memory
(see the Protecting the Flash section). Clearing the bits enables the protection.
PROTB0.7
PROTB0.6
PROTB0.5
PROTB0.4
PROTB0.3
PROTB0.2
PROTB0.1
PROTB0.0
Page 7
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Page 5
Page 4
Page 3
Page 2
Page 1
Page 0
Table 93. Flash Write/Erase Protection 1 SFR (PROTB1, 0xBE)
Bit No.
Mnemonic
Default
Description
7 to 0
PROTB1
0xFF
This SFR is used to write the write/erase protection bits for Page 8 to Page15 of the flash memory
(see the Protecting the Flash section). Clearing the bits enables the protection.
PROTB1.7
PROTB1.6
PROTB1.5
PROTB1.4
PROTB1.3
PROTB1.2
PROTB1.1
PROTB1.0
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