EVAL-ADE7569F16EB datasheet(70/136 Pages) AD

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ADE7566/ADE7569

Preliminary Technical Data

Rev. PrA | Page 70 of 136

8052 MCU CORE ARCHITECTURE

The ADE7566/ADE7569 have an 8052 MCU core and use the

8051 instruction set. Some of the standard 8052 peripherals,

such as the UART, have been enhanced. This section describes

the standard 8052 core and its enhancements used in the

ADE7566/ADE7569.

The special function register (SFR) space is mapped into the

upper 128 bytes of internal data memory space and is accessed

by direct addressing only. It provides an interface between the

CPU and all on-chip peripherals. A block diagram showing the

programming model of the ADE7566/ADE7569 via the SFR

area is shown in Figure 67.

All registers except the program counter (PC), instruction

reside in the SFR area. The SFR registers include power

control, configuration, and data registers that provide an

interface between the CPU and all on-chip peripherals.

ENERGY

MEASUREMENT

16kB ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE

PROGRAM/DATA

MEMORY

8051

COMPATIBLE

CORE

256 BYTES XRAM

OTHER ON-CHIP

PERIPHERALS:

SERIAL I/O

WDT

TIMERS

BATTERY

ADC

LCD DRIVER

TEMPERATURE

ADC

RTC

POWER

MANAGEMENT

128-BYTE

SPECIAL

FUNCTION

AREA

STACK

256 BYTES

GENERAL

PURPOSE

RAM

BANKS

Figure 67. ADE7566/ADE7569 Block Diagram

MCU REGISTERS

The registers used by the MCU are summarized in this section.

Table 52. 8051 SFRs

SFR

Address

Bit Addressable

Description

0xE0

Yes

Accumulator.

0xF0

Yes

Auxiliary Math Register.

PSW

0xD0

Yes

Program Status Word (see Table 53).

PCON

0x87

Power Control Register (see Table 54).

DPL

0x82

Data Pointer LSByte (see Table 55).

DPH

0x83

Data Pointer MSByte (see Table 56).

DPTR

0x83 and 0x82

16-Bit Data Pointer (see Table 57).

0x81

Stack Pointer LSByte (see Table 58).

CFG

0xAF

Configuration (see Table 59).

Table 53. Program Status Word SFR (PSW, 0xD0)

Bit No.

Address

Mnemonic

Description

0xD7

Carry Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.

0xD6

Auxiliary Carry Flag. Modified by ADD and ADDC instructions.

0xD5

General-Purpose Flag Available to the User.

RS1

RS0

Result (Selected Bank)

4 to 3

0xD4, 0xD3

RS1, RS0

0xD2

Overflow Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.

0xD1

General-Purpose Flag Available to the User.

0xD0

Parity Bit. The number of bits set in the accumulator added to the value of the parity bit is always an

even number.

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