ST72E121 datasheet(30/92 Pages) STMICROELECTRONICS

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ST72E121 ST72T121

4.2 WATCHDOG TIMER (WDG)

4.2.1 Introduction

The Watchdog timer is used to detect the occur-

rence of a software fault, usually generated by ex-

ternal interference or by unforeseen logical condi-

tions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the counter’s contents before the T6 bit be-

comes cleared.

4.2.2 Main Features

Programmable timer (64 increments of 12288

CPU cycles)

Programmable reset

Reset (if watchdog activated) after a HALT

instruction or when the T6 bit reaches zero

Hardware Watchdog selectable by option byte

Watchdog Reset indicated by status flag (in

versions with Safe Reset option only)

4.2.3 Functional Description

The counter value stored in the CR register (bits

T[6:0]), is decremented every 12,288 machine cy-

cles, and the length of the timeout period can be

programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T[6:0]) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle pulling low the reset pin for typically

500ns.

Figure 20. Watchdog Block Diagram

RESET

WDGA

7-BIT DOWNCOUNTER

fCPU

CLOCK DIVIDER

WATCHDOG CONTROL REGISTER (CR)

÷12288

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