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ST72E121 Fiches technique(PDF) 85 Page - STMicroelectronics

No de pièce ST72E121
Description  8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS
PDF  92 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72E121 Fiches technique(HTML) 85 Page - STMicroelectronics

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ST72E121 ST72T121
PERIPHERAL CHARACTERISTICS (Cont’d)
Measurement points are VOL,VOH,VIL and VIH in the SPI Timing Diagram
Figure 42. SPI Master Timing Diagram CPHA=0, CPOL=0
Serial Peripheral Interface
Ref.
Symbol
Parameter
Condition
Value
Unit
Min.
Max.
fSPI
SPI frequency
Master
Slave
1/128
dc
1/4
1/2
fCPU
1tSPI
SPI clock periode
Master
Slave
4
2
tCPU
2tLead
Enable lead time
Slave
120
ns
3tLag
Enable lag time
Slave
120
ns
4tSPI_H
Clock (SCK) high time
Master
Slave
100
90
ns
5tSPI_L
Clock (SCK) low time
Master
Slave
100
90
ns
6tSU
Data set-up time
Master
Slave
100
100
ns
7tH
Data hold time (inputs)
Master
Slave
100
100
ns
8tA
Access time (time to data active
from high impedance state)
Slave
0
120
ns
9tDis
Disable time (hold time to high im-
pedance state)
240
ns
10
tV
Data valid
Master (before capture edge)
Slave (after enable edge)
0.25
120
tCPU
ns
11
tHold
Data hold time (outputs)
Master (before capture edge)
Slave (after enable edge)
0.25
0
tCPU
ns
12
tRise
Rise time
(20% VDD to 70% VDD,CL = 200pF)
Outputs: SCK,MOSI,M ISO
Inputs: SCK,MOSI ,MISO, SS
100
100
ns
µs
13
tFall
Fall time
(70% VDD to 20% VDD,CL = 200pF)
Outputs: SCK,MOSI,M ISO
Inputs: SCK,MOSI ,MISO, SS
100
100
ns
µs
1
6
7
10
11
12
13
SS
(INPUT)
SCK
(OUTPUT)
MISO
MOSI
(INPUT)
(OUTPUT)
45
D7-OUT
D6-OUT
D0-OUT
D7-IN
D6-IN
D0-IN
VR000109
85



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