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©2019-2023 Renesas Electronics Corporation

R31DS0029EU0601 September 13, 2023

XF Datasheet

Revision History

Date

Description of Change

September 13, 2023

Changed MSL level to “3” from “does not apply” in Table 5.

February 10, 2022

▪ Updated Output Clock Duty Cycle minimum and maximum specifications for LVDS, LVPECL, HCSL, and

CML in Table 15, Table 16, and Table 17.

July 13, 2021

▪ Update Ordering Information (XO) key (precision specification).

May 10, 2021

▪ Updated Package and Precision codes in VCXO Ordering Information table.

▪ Moved XO and VCXO Ordering Information tables to follow Pin Descriptions.

▪ Updated VCXO Precision options from H, J, and K to X, Y, and Z, updated VCXO bandwidth values.

March 31, 2021

▪ Updated title of Ordering Information table to include (XO).

▪ Added a new Ordering Information table for (VCXO).

▪ Updated Frequency Tolerance values.

February 11, 2021

Added new package options: 5.0 × 3.2 mm and 3.2 × 2.5 mm.

January 6, 2020

Updated notes for pin descriptions.

July 22, 2019

Updated LVDS Differential Output Voltage minimum value from 0.28V to 0.30V.

May 22, 2019

Changed 3.3V, 2.5V, and 1.8V LVPECL current consumption conditions value from 670MHz to 2.1GHz.

April 3, 2019

Initial release.