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PSD833F2 Fiches technique(PDF) 94 Page - STMicroelectronics

No de pièce PSD833F2
Description  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  110 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD833F2 Fiches technique(HTML) 94 Page - STMicroelectronics

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PSD835G2
PSD8XX Family
93
-90
-12
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
tLVDV
ALE Access Time from
Power Down
128
135
ns
Maximum Delay from APD Enable
tCLWH
to Internal PDN Valid Signal
Using CLKIN Input
15 * tCLCL (µs) (Note 1)
µs
Power Down Timing (3.0 V to 3.6 V Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tNLNH
Warm RESET Active Low Time (Note 1)
300
ns
tOPR
RESET High to Operational Device
300
ns
tNLNH-PO
Power On Reset Active Low Time
1
ms
Warm RESETActive Low Time
tNLNH-A
(Note 2)
25
µs
Reset Pin Timing (3.0 V to 3.6 V Versions)
NOTE: 1. tCLCL is the CLKIN clock period.
Microcontroller Interface – PSD835G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
Vstby Detection to Vstbyon Output
High
(Note 1)
20
µs
tBXBL
Vstby Off Detection to Vstbyon
Output Low
(Note 1)
20
µs
Vstbyon Timing (3.0 V to 3.6 V Versions)
NOTE: 1. RESET will not abort Flash programming/erase cycles.
2. RESET will abort Flash programming or erase cycle.
NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.



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