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R7KA8M2AFDCAM Fiches technique(PDF) 151 Page - Renesas Technology Corp |
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R7KA8M2AFDCAM Fiches technique(HTML) 151 Page - Renesas Technology Corp |
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151 / 295 page ![]() ACMPHSn edge detection signal (n = 0 to 5) GPT PWM output pins Outputs disabled tPOEGDC Figure 2.57 Output Disable Time for POEG in Response to Edge Detection Signal from a Comparator GPT PWM output pins Outputs disabled tPOEGDS POEGGn.SSF bit (n = A to D) Figure 2.58 Output Disable Time for POEG in Response to the Register Setting Oscillation stop detection signal (internal signal) GPT PWM output pins Outputs disabled tPOEGDOS Main clock Figure 2.59 Output Disable Time of POEG in Response to the Oscillation Stop Detection ACMPHSn level detection signal (n = 0 to 5) GPT PWM output pins Outputs disabled tPOEGDDC Figure 2.60 Output Disable Time for POEG in Response to Level Detection Signal from a Comparator RA8M2 Datasheet 2. Electrical Characteristics R01DS0438EJ0130 Rev.1.30 Feb 27, 2026 Page 151 of 295 |
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