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STMPE801 Fiches technique(PDF) 9 Page - STMicroelectronics |
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STMPE801 Fiches technique(HTML) 9 Page - STMicroelectronics |
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9 / 26 page ![]() STMPE801 I2C module 9/26 5 I2C module STMPE801 is interface to the main processor using an I2C bus. 5.1 I2C address Addressing scheme of STMPE801 is designed to allow up to 2 devices to be connected to the same I2C bus. Figure 3. Addressing scheme For the bus master to communicate to the slave device, the bus master must initiate a Start condition anf followed by the slave device address. Accompanying the slave device address, there is a Read/Write bit (R/W). The bit is set to 1 for Read and 0 for write operation. If a match occurs on the slave device address, the corresponding device gives an acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not responding to the transaction. Table 6. Addresses ADDR0 Address Note 0 0x82 1 0x88 |
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