CS5460 datasheet(11/34 Pages) CIRRUS

11 / 34 page

CS5460

DS279PP5

2.2.1 Single Computation Cycle (C = 0)

Based on the information provided in the Cycle

Count register, a single computation cycle is per-

formed after the user transmits the single conver-

sion cycle command. After the computations are

complete, DRDY is set. Thirty-two SCLKs are

then needed to acquire a calculation result. The first

8 SCLKs are used to clock in the command to de-

termine which result register is to be read. The last

24 SCLKs are needed to read the desired calcula-

tion result register. After reading the data, the serial

port returns to the command mode, where it waits

for a new command to be issued.

2.2.2 Multiple Computation Cycles (C = 1)

Based on the information provided in the Cycle

Count register, continuous computation cycles are

repeatedly performed on the voltage and current

cycles. Computation cycles cannot be start-

ed/stopped on a per channel basis. After each com-

putation cycle is completed, DRDY is set.

Thirty-two SCLKs are then needed to read a regis-

ter. The first 8 SCLKs are used to clock in the com-

mand to determine which results register is to be

read. The last 24 SCLKs are needed to read the cal-

culation result. While in this mode, the user may

choose to acquire only the calculations required for

the application as DRDY rises and falls to indicate

the availability of a new data.

The RMS calculations require a Sinc2 operation

prior to their square root operation. Therefore, the

first output for each channel will be invalid (i.e. all

RMS calculations are invalid in the single compu-

tation cycle routine and the first RMS calculations

will be invalid in the continuous computation cy-

cle). All energy calculations will be valid since en-

ergy calculations don’t require this Sinc2 operation.

2.3 High Rate Digital Filters

The high rate filter on the voltage channel is imple-

mented as a fixed sinc2 filter, compensated by a

short length FIR. When the converter is driven with

a 4.096 MHz clock (K=1), the filter has a magni-

tude response similar to that shown in Figure 6.

Note that the filter’s response scales with MCLK

frequency and K.

The current channel contains a sinc4 filter, compen-

sated by a short length FIR. When the converter is

driven with a 4.096 MHz clock (K=1) the compos-

ite filter response is given in Figure 7.

VOLTAGE

∆Σ

SINC2

off

CURRENT

SINC4

off

TBC *

DELAY

REG

DELAY

REG

FIR

HPF

APF

Configuration Register *

PC[3:0] Bits

RMS

÷4096

E to F

E *

out

dir

PULSE-RATE*

* DENOTES REGISTER NAME

∆Σ

HPF

APF

FIR

SINC2

I *

P *

SINC2

Figure 5. Data Flow.

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