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MPC8309CVMADDC Fiches technique(PDF) 11 Page - NXP Semiconductors |
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MPC8309CVMADDC Fiches technique(HTML) 11 Page - NXP Semiconductors |
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11 / 81 page ![]() MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 11 Power Characteristics Figure 3. MPC8309 Power-Up Sequencing Example 3 Power Characteristics The typical power dissipation for this family of MPC8309 devices is shown in the following table. Table 5. MPC8309 Power Dissipation Core Frequency (MHz) QUICC Engine Frequency (MHz) CSB Frequency (MHz) Typical Maximum Unit Note 266 233 133 0.341 0.920 W 1, 2, 3 333 233 133 0.361 0.938 W 1, 2, 3 400 233 133 0.381 0.969 W 1,2,3 417 233 167 0.429 1.003 W 1,2,3 Notes: 1. The values do not include I/O supply power (OVDD and GVDD), but it does include VDD and AVDD power. For I/O power values, see Table 6. 2. Typical power is based on a nominal voltage of VDD = 1.0 V, ambient temperature, and the core running a Dhrystone benchmark application. The measurements were taken on the evaluation board using WC process silicon. 3. Maximum power is based on a voltage of VDD = 1.05 V, WC process, a junction TJ = 105C, and a smoke test code. t 90% V Core Voltage (VDD) I/O Voltage (GVDD and OVDD) 0 0.7 V PORESET >= 32 tSYS_CLK_IN / PCI_SYNC_IN |
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