MPC8309CVMADDC datasheet(65/81 Pages) NXP

No de pièce	MPC8309CVMADDC

Description	PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications

PDF	81 Pages

Scroll/Zoom	100%

Fabricant	NXP [NXP Semiconductors]

Site Internet	http://www.nxp.com

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Clocking

23 Clocking

The following figure shows the internal distribution of clocks within the MPC8309.

Figure 45. MPC8309 Clock Subsystem

The primary clock source for the MPC8309 can be one of three inputs,Crystal(SYS_XTAL_IN ),

SYS_CLK_IN or PCI_SYNC_IN, depending on whether the device is configured in PCI host or PCI agent

mode, respectively.

Core PLL

System

LBC

LCLK[0:1]

core_clk

e300c3 core

csb_clk

Local Bus

Clock

Unit

of the device

lbc_clk

Memory

Device

Clock

MEMC_MCK

DDR

ddr_clk

DDR

Memory

Device

PLL

to DDR

memory

controller

Clock

Divider

QE PLL

CLK Gen

QE Block

qe_clk

QE_CLK_IN

PCI Clock Divider

csb_clk

to rest

to local bus

CFG_CLKIN_DIV

PCI_SYNC_OUT

PCI_CLK[0:2]

PCI_SYNC_IN

MPC8309

Rest of the System

SYS_XTAL_OUT

SYS_XTAL_IN

SYS_CLK_IN

CRYSTAL

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