TDA7564BPD datasheet(22/34 Pages) STMICROELECTRONICS

22 / 34 page

I2C bus interface

TDA7564B

22/34

Doc ID 12734 Rev 4

I2C bus interface

Data transmission from microprocessor to the TDA7564B and vice versa takes place

through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up

resistors to positive supply voltage must be connected).

8.1

Data validity

As shown by Figure 30, the data on the SDA line must be stable during the high period of

the clock. The high and low state of the data line can only change when the clock signal on

the SCL line is LOW.

8.2

Start and stop conditions

As shown by Figure 31 a start condition is a high to low transition of the SDA line while SCL

is high. The stop condition is a low to high transition of the SDA line while SCL is high.

8.3

Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an

acknowledge bit. The MSB is transferred first.

8.4

Acknowledge

The transmitter* puts a resistive high level on the SDA line during the acknowledge clock

pulse (see Figure 32). The receiver** the acknowledges has to pull-down (low) the SDA line

during the acknowledge clock pulse, so that the SDA line is stable low during this clock

pulse.

* Transmitter

–master (

P) when it writes an address to the TDA7564B

–

slave (TDA7564B) when the

P reads a data byte from TDA7564B

** Receiver

–

slave (TDA7564B) when the

P writes an address to the TDA7564B

–

master (µP) when it reads a data byte from TDA7564B

Figure 30. Data validity on the I2C bus

SDA

SCL

DATA LINE

STABLE, DATA

VALID

CHANGE

DATA

ALLOWED

D99AU1031

TDA7564BPD Fiches technique(PDF) 22 Page - STMicroelectronics

TDA7564BPD Fiches technique(HTML) 22 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Fiches technique Télécharger

Lien URL