PIC16F1507-ESLASHSS. datasheet(223/278 Pages) MICROCHIP

223 / 278 page

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DS40001586D-page 223

PIC16(L)F1507

FIGURE 25-11:

CLC PROPAGATION TIMING

TABLE 25-12: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max. Units

Conditions

CLC01* TCLCIN

CLC input time

—

CLC02* TCLC

CLC module input to output propagation time

—

VDD = 1.8V

VDD > 3.6V

CLC03* TCLCOUT CLC output time

Rise Time

—

OS18

—

(Note 1)

Fall Time

—

OS19

—

(Note 1)

CLC04* FCLCMAX CLC maximum switching frequency

—

MHz

These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1:

See Table 25-9 for OS18 and OS19 rise and fall times.

LCx_in[n]

(1)

CLC

Output time

CLC

Input time

LCx_out

(1)

CLCx

CLCxINn

CLC

Module

CLC01

CLC02

CLC03

LCx_in[n]

(1)

CLC

Output time

CLC

Input time

LCx_out

(1)

CLCx

CLCxINn

CLC

Module

Rev. 10-000031A

7/30/2013

Note 1:

See FIGURE 20-1:, Configurable Logic Cell Block Diagram, to identify specific CLC signals.

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