RH3

56

—

—

—

—

—

—

—

—

—

—

—

—

—

—

VDD

10, 38

—

—

—

—

—

—

—

—

—

—

—

—

—

—

VSS

9, 41

—

—

—

—

—

—

—

—

—

—

—

—

—

—

OUT(2)

—

ADGRDA

ADGRDB

—

C1OUT

C2OUT

C3OUT

—

SDO1

SCK1

SDO2

SCK2

TX1/CK1(3)

DT1(3)

TX2/CK2(3)

DT2(3)

TX3/CK3(3)

DT3(3)

TX4/CK4(3)

DT4(3)

TX5/CK5(3)

DT5(3)

DSM

TMR0

—

CCP1

CCP2

CCP3

CCP4

CCP5

PWM6OUT

PWM7OUT

CWG1A

CWG1B

CWG1C

CWG1D

CLKR

—

—

TABLE 5:

64-PIN ALLOCATION TABLE PIC18(L)F6XK40 (CONTINUED)

Note

1:

This is a PPS remappable signal. The input function may be removed from the default location shown to one of several other PORTx pins. Details about this can be found in the data sheet.

2:

All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several POTRTx pin options. Details about this can be found in the data sheet.

3:

This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.

4:

These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be

standard TTL/ST as selected b the INLVL register, instead of the I2C specific input buffer thresholds.