LP3923

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SNVS567B – APRIL 2010 – REVISED MAY 2013

Charger Electrical Characteristics (continued)

Unless otherwise noted, VCHG_IN = 5V, VIN= BATT = 3.6V, CCHG_IN = 1 μF, VBATT = 30 µF. Typical values and limits appearing

in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for

operation, TA = TJ = −25°C to +85°C.

(1)(2)

Symbol

Parameter

Conditions

Typical

Limit

Units

Min

Max

IEOC

End-of-charging

0.1C option selected

10

%

current, % of full-rate

current

VRESTART

Restart threshold voltage

From VTERM voltage (4.2V, −100 mV options

−100

−70

−130

mV

selected)

IMON

IMON Voltage 1

ICHG = 100 mA

0.247

V

IMON Voltage 2

ICHG = 400 mA

0.988

0.840

1.127

CBATT

Capacitance on BATT

See(4)

30

1000

µF

TREG

Regulated junction

See(4)

115

°C

temperature

Detection and Timing (one combined timer)

TPOK

Power OK deglitch time

VCHG > VBATT + VOK_CHG

30

ms

TPC_FULL

Deglitch time

From pre-charging to full-rate charging

210

ms

TCHG

Charge timer

Pre-charge mode

1

disabled

2

Hrs

CC mode/CV mode (combined timer)

5

8

TEOC

Deglitch time for end- of-

210

ms

charge transition

(4)

Ensured by design.

Serial Interface

Unless otherwise noted, VIN = BATT = 3.6V, GND = 0V, CVIN1–2 = 10 µF CLDOx = 1 µF and VLDO3 = 3.0V. Typical values and

limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction

temperature range for operation, TA = TJ = −40°C to +125°C.

(1) (2)

Limit

Unit

Symbol

Parameter

Conditions

Typ

s

Min

Max

fCLK

Clock Frequency

400

kHz

tBF

Bus-Free Time between START and STOP

1.3

µs

tHOLD

Hold Time Repeated START Condition

0.6

µs

tCLK-LP

CLK Low Period

1.3

µs

tCLK-HP

CLK High Period

0.6

µs

tSU

Set-Up Time Repeated START Condition

0.6

µs

tDATA-HOLD

Data Hold Time

50

ns

tDATA-SU

Data Set-Up Time

100

ns

tSU

Set-Up Time for STOP Condition

0.6

µs

tTRANS

Maximum Pulse Width of Spikes that Must Be

Suppressed by the Input Filter of Both DATA & CLK

50

ns

Signals

(1)

All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot

and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical

process control.

(2)

Ensured by design.

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