TDA7546 datasheet(50/68 Pages) STMICROELECTRONICS

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Software specifications

TDA7546

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6.3

RDS decoder software specification

6.3.1

Programming through serial bus interface

The serial bus interface is used to access the different registers of the chip. It is able to

handle both I2C and

SPI transfer protocols, the selection between the two modes is done thanks to the pin CSN:

–

if the pin CSN is high, the interface operates as an I2C bus.

–

if the pin CSN is asserted low, the interface operates as a SPI bus.

In both modes, the device is a slave, i.e the clock pin SCL_CLK is only an input for the chip.

Depending on the transfer mode, external pins have alternate functions as following:

13 registers are available with read or read/write access:

The meaning of each bit is described below:

Table 35.

External pins alternate functions

function in SPI mode (CSN=0)

function in I2C mode (CSN=1)

SCL_CLK

CLK (serial clock)

SCL (serial clock)

SDA_DATAIN

DATAIN (data input)

SDA (data line)

SA_DATAOUT

DATAOUT (data output)

SA (slave address)

Table 36.

Registers description

access

rights

function

rds_int[7:0]

read/write

interrupt source setting, synch., bne information

rds_qu[7:0]

read

quality counter, actual block name

rds_corrp[7:0]

read

error correction status, buffer ovf information

rds_bd_h[7:0]

read

high byte of current RDS block

rds_bd_l[7:0]

read

low byte of current RDS block

rds_bd_ctrl[7:0]

read/write

frequency, quality sensitivity, demodulator pll settings

sinc4reg[7:0]

read/write

sinc4 filter settings (for internal use only)

testreg[7:0]

read/write

test modes (for internal use only)

pllreg4[7:0]

read/write

PLL control register 4

pllreg3[7:0]

read/write

PLL control register 3

pllreg2[7:0]

read/write

PLL control register 2

pllreg1[7:0]

read/write

PLL control register 1

pllreg0[7:0]

read/write

PLL control register 0

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