AX88172ATF datasheet(28/45 Pages) ASIX

28 / 45 page

ASIX ELECTRONICS CORPORATION

AX88772A/AX88172A

Low-pin-count

USB 2.0 to 10/100M Fast Ethernet Controller

9.4 AC Timing Characteristics

Notice that the following AC timing specifications for output pins are based on CL (Output

load)=50pF.

9.4.1

Clock Timing

XTL12P

TP_XTL12P

TH_XTL12P

TL_XTL12P

Symbol

Parameter

Condition

Min

Typ

Max

Unit

TP_XTL12P XTL12P clock cycle time

83.33

TH_XTL12P XTL12P clock high time

41.6

TL_XTL12P XTL12P clock low time

41.6

XTL25P

TP_XTL25P

TH_XTL25P

TL_XTL25P

Symbol

Parameter

Condition

Min

Typ

Max

Unit

TP_XTL25P XTL25P clock cycle time

40.0

TH_XTL25P XTL25P clock high time

20.0

TL_XTL25P XTL25P clock low time

20.0

9.4.2

Reset Timing

XTL12P

RESET_N

Symbol

Description

Min

Typ

Max

Unit

Trst

Reset pulse width after XTL12P is running

120000 XTL12P clock cycle*

*: If the system applications require using hardware reset pin, RESET_N, to reset AX88772A/AX88172A during device

initialization or normal operation after VBUS pin is asserted, the above timing spec (Min=5μs, Max=10ms) of

RESET_N should be met.

VIH

VIL

VIH

VIL

Trst

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