TUSB1044AI datasheet(23/66 Pages) TI1

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7.3.5 Receiver Linear Equalization

The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference

in the system. The receiver overcomes these losses by attenuating the low-frequency components of the

signals with respect to the high-frequency components. Select the proper gain setting to match the channel

insertion loss. Two 4-level input pins enable up to 16 possible equalization settings. The upstream path

and the downstream path each have two 4-level inputs for equalization settings; UEQ[1:0] and DEQ[1:0]

respectively. The TUSB1044A also provides the flexibility of adjusting equalization settings through I2C registers

URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL for each individual channel and

for each direction (upstream or downstream).

7.4 Device Functional Modes

7.4.1 Device Configuration in GPIO Mode

The TUSB1044A is in GPIO configuration when I2C_EN = 0 or I2C_EN = F. The TUSB1044A supports

operational combinations with USB and two different Type-C Alternate Modes. One combination includes USB

and Alternate Mode DisplayPort, and the other combination includes USB and custom Alternate Mode. For each

operational combination, the data path directions can be further set using the DIR[1:0] pins or through I2C to

enable the device to operate in the source or sink sides. See also Table 7-3.

When the device is set to operate in a USB and Alternate Mode DisplayPort, the following configurations can

be further set: USB3.2 only, two DisplayPort lanes + USB3.2, or four DisplayPort lanes (no USB3.2). The CTL1

pin controls whether DisplayPort mode is enabled. The combination of CTL1 and CTL0 selects between USB3.2

only, twolanes of DisplayPort, or four lanes of DisplayPort as detailed in Table 7-3. The AUXP/N to SBU1/2

mapping is controlled based on Table 7-4.

When the device is set to operate in a USB and custom Alternate Mode, the following configurations can be

further set: USB3.2 only, two channels of custom Alternate Mode + USB3.2, or four channels of custom Alternate

Mode (no USB3.2). The CTL1 pin controls whether custom Alternate Mode is enabled. The combination of CTL1

and CTL0 selects between USB3.2 only, two channels of custom Alternate Mode, or four channels of custom

Alternate Mode as detailed in Table 7-3. The AUXP/N to SBU1/2 mapping is controlled based on Table 7-4.

Further data path direction control can be achieved using the SWAP pin. When set high, the SWAP pin reverses

the data path direction on all the channels and swaps the equalization settings of the upstream and downstream

facing input ports. This pin can be useful in active cable application with the TUSB1044A installed on only one

end. The SWAP pin can be set based on which cable end is plugged to the source or sink side receptacle

After power-up (VCC from 0V to 3.3V), the TUSB1044A defaults to USB3.2 mode. The USB PD controller, upon

detecting no device attached to Type-C port or USB3.2 operation not required by attached device, must take the

TUSB1044A out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.

Table 7-3. GPIO Configuration Control

DIR1

DIR0

CTL1

CTL0

FLIP

TUSB1044A CONFIGURATION

VESA® DisplayPort™ ALT

MODE

DFP_D CONFIGURATION

USB + DisplayPort Alternate Mode (Source Side)

Power Down

—

Power Down

—

One Port USB 3.2 - No Flip

—

One Port USB 3.2 – With Flip

—

4-Lane DP - No Flip

C and E

4-Lane DP – with Flip

C and E

One Port USB 3.2 + 2-Lane DP- No

Flip

D and F

One Port USB 3.2 + 2-Lane DP– with

Flip

D and F

USB + DisplayPort Alternate Mode (Sink Side)

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TUSB1044A

SLLSG07 – MARCH 2025

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