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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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UPSD3422EB40U6 Fiches technique(PDF) 161 Page - STMicroelectronics |
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UPSD3422EB40U6 Fiches technique(HTML) 161 Page - STMicroelectronics |
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161 / 293 page  uPSD34xx USB interface 161/293 ● USB OUT FIFO Interrupt Flag (UIF2) The USB OUT FIFO Interrupt Flag register (see Table 78) contains flags that indicate when an OUT Endpoint FIFO that was empty becomes full. Once set, firmware must clear the flag by writing a '0' to the appropriate bit. When FIFOs are paired, only the odd numbered FIFO Interrupt flags are active. Table 78. USB OUT FIFO interrupt flag (UIF2 0EAh, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – OUT4F OUT3F OUT2F OUT1F OUT0F Bit Symbol R/W Definition 7 – – Reserved 6 – – Reserved 5 – – Reserved 4OUT4F R/W Endpoint 4 OUT FIFO Interrupt flag This bit is set when the FIFO status changes from empty to full. 3OUT3F R/W Endpoint 3 OUT FIFO Interrupt flag This bit is set when the FIFO status changes from empty to full. 2OUT2F R/W Endpoint 2 OUT FIFO Interrupt flag This bit is set when the FIFO status changes from empty to full. 1OUT1F R/W Endpoint 1 OUT FIFO Interrupt flag This bit is set when the FIFO status changes from empty to full. 0OUT0F R/W Endpoint 0 OUT FIFO Interrupt flag This bit is set when the FIFO status changes from empty to full. |
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