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UPSD3422EB40U6 Fiches technique(PDF) 54 Page - STMicroelectronics |
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UPSD3422EB40U6 Fiches technique(HTML) 54 Page - STMicroelectronics |
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54 / 293 page ![]() Interrupt system uPSD34xx 54/293 Note: 1 See USB interrupt flag registers UIF0-3. Figure 13. Enabling and polling interrupts PCA 11 005Bh OFVx, INTFx (PCASTA[0:7]) No EPCA (IEA.5) PPCA (IPA.5) UART1 12 (low) 004Bh RI (SCON1.0) TI (SCON1.1) No ES1 (IEA.4) PS1 (IPA.4) Interrupt Source Polling Priority Vecto r Addr Flag Bit Name (SFR.bit position) 1 = Intr Pending 0 = No Interrupt Flag Bit Auto- Cleared by Hardware? Enable Bit Name (SFR.bit position) 1 = Intr Enabled 0 = Intr Disabled Priority Bit Name (SFR.bit position) 1= High Priority 0 = Low Priority Reserved Ext INT0 Ext INT1 Timer 0 UART0 Timer 1 SPI USB Timer 2 High Low Interrupt Sources IE/IEA IP/IPA Priority Global Enable ADC PCA I 2C UART1 AI07844 |
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