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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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UPSD3422EB40U6 Fiches technique(PDF) 160 Page - STMicroelectronics |
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UPSD3422EB40U6 Fiches technique(HTML) 160 Page - STMicroelectronics |
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160 / 293 page  USB interface uPSD34xx 160/293 ● USB IN FIFO Interrupt Flag (UIF1) The USB IN FIFO Interrupt Flag register (see Table 77) contains flags that indicate when an IN Endpoint FIFO that was full becomes empty. Once set, firmware must clear the flag by writing a '0' to the appropriate bit. When FIFOs are paired, only the odd numbered FIFO Interrupt flags are active. Table 77. USB IN FIFO interrupt flag (UIF1 0E9h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – IN4F IN3F IN2F IN1F IN0F Bit Symbol R/W Definition 7 – – Reserved 6 – – Reserved 5 – – Reserved 4IN4F R/W Endpoint 4 IN FIFO Interrupt flag This bit is set when the FIFO status changes from full to empty. 3IN3F R/W Endpoint 3 IN FIFO Interrupt flag This bit is set when the FIFO status changes from full to empty. 2IN2F R/W Endpoint 2 IN FIFO Interrupt flag This bit is set when the FIFO status changes from full to empty. 1IN1F R/W Endpoint 1 IN FIFO Interrupt flag This bit is set when the FIFO status changes from full to empty. 0IN0F R/W Endpoint 0 IN FIFO Interrupt flag This bit is set when the FIFO status changes from full to empty. |
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