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HE84770D

HE80000 SERIES

August 7, 2006

Page 4 of 29

V1.2

This specification is subject to change without notice. Please contact sales person for the latest version before use.

Pin Name

Pin #

I/O

Description

will turn on the key scan function.

PRT14[7..0]/

SEG[23:16]

26 ~ 33

B/

O

8-bit bi-directional I/O port 14 is shared with LCD segment pads SEG[23..16]. The

function of the pad can be selected individually by mask options MO_LIO14[7..0].

(‘1’ for LCD and ‘0’ for I/O).

The output type of I/O pad can also be selected by mask option MO_14PP[7..0] (1 for

push-pull and ‘0’ for open-drain).

As the output structure of I/O pad does not contain tri-state buffer. When using the I/O

as input, “1” must be outputted before reading.

PRT15[7..0]/

SEG[15:8]

34 ~ 41

B/

O

8-bit bi-directional I/O port 15 is shared with LCD segment pads SEG[15..8]. The

function of the pad can be selected individually by mask options MO_LIO15[7..0].

(‘1’ for LCD and ‘0’ for I/O).

The output type of I/O pad can also be selected by mask option MO_15PP[7..0] (1 for

push-pull and ‘0’ for open-drain).

As the output structure of I/O pad does not contain tri-state buffer. When using the I/O

as input, “1” must be outputted before reading.

PRT17[7..0]/

SEG[7:0]

42 ~ 49

B/

O

8-bit bi-directional I/O port 17 is shared with LCD segment pads SEG[7..0]. The

function of the pad can be selected individually by mask options MO_LIO17[7..0].

(‘1’ for LCD and ‘0’ for I/O).

The output type of I/O pad can also be selected by mask option MO_17PP[7..0] (1 for

push-pull and ‘0’ for open-drain).

As the output structure of I/O pad does not contain tri-state buffer. When using the I/O

as input, “1” must be outputted before reading.

COM[31..0]

50 ~ 81 O LCD COMMON Driver pads.

LVL1

82

P

LCD Bias Voltage 1.

LVL2

83

P

LCD Bias Voltage 2

LVL3

84

P

LCD Bias Voltage 3

LVL4

85

P

LCD Bias Voltage 4

LVL5

86

P

LCD Bias Voltage 5.

LGS2

87

I

LCD Drive Voltage Setting

LVP

88

P

Charge Pump Output..

LCAP4A

89

O Charge Pump Capacitor Pin.

LCAP2B

90

O Charge Pump Capacitor Pin.

LCAP2A

91

O Charge Pump Capacitor Pin.

LCAP1A

92

O Charge Pump Capacitor Pin.

LCAP1B

93

O Charge Pump Capacitor Pin.

LCAP3A

94

O Charge Pump Capacitor Pin.

LVREG

95

O Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns

pumped to LVP. Adjust resistor between LGS1 and LVREG to set LVREG voltage.

LGS1

96

I

Regulator Voltage Setting

LVAG

97

O Reference Voltage Output. Fixed 0.9 Volt DC reference voltage

GND

98

P

Power ground Input.

VO

99

O

DAC Voice Output. Set the bit 1 and clear the bit 0 of VOC (DA = ‘1’ and OP = ‘0’)

register to turn on DAC with VO output.

DAO

100

O

Alternate output of DAC. Set both bit 1 and bit 0 of VOC register (DA = ‘1’ and OP =

‘1’) to turn on DAC with DAO output as well as OP comparator.

OPIN

101

I

Inverting input of OP Amp. Set the bit 0 of VOC register (OP = ‘1’) to turn on OP

comparator.

OPIP

102

I

Non-inverting input of OP Amp.

OPO

103

O Output of OP Amp.

RSTP_N

104

I

System Reset input pin. Level trigger, active low on this pin will put the chip in reset

state.

FXO,

105, 106 O, External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (‘0’