ST7263BDX datasheet(87/145 Pages) STMICROELECTRONICS

No de pièce	ST7263BDX

Description	Low speed USB 8-bit MCU family with up to 32K Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI & I짼C

PDF	145 Pages

Scroll/Zoom	100%

Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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ST7263BDx ST7263BHx ST7263BKx ST7263BE

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I²C bus interface (Cont’d)

Acknowledge may be enabled and disabled by

software.

The I²C interface address and/or general call ad-

dress can be selected by software.

The speed of the I²C interface may be selected be-

tween Standard (up to 100kHz) and Fast I²C (up to

400kHz).

SDA/SCL Line Control

Transmitter mode: the interface holds the clock

line low before transmission to wait for the micro-

controller to write the byte in the Data Register.

Receiver mode: the interface holds the clock line

low after reception to wait for the microcontroller to

read the byte in the Data Register.

The SCL frequency (FSCL) is controlled by a pro-

grammable clock divider which depends on the I²C

bus mode.

When the I²C cell is enabled, the SDA and SCL

ports must be configured as floating inputs. In this

case, the value of the external pull-up resistor

used depends on the application.

When the I²C cell is disabled, the SDA and SCL

ports revert to being standard I/O port pins.

Figure 44. I²C Interface block diagram

DATA REGISTER (DR)

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER (OAR)

CLOCK CONTROL REGISTER (CCR)

STATUS REGISTER 1 (SR1)

CONTROL REGISTER (CR)

CONTROL LOGIC

STATUS REGISTER 2 (SR2)

INTERRUPT

CLOCK CONTROL

DATA CONTROL

SCL or SCLI

SDA or SDAI

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