M58PR256J datasheet(14/114 Pages) STMICROELECTRONICS

14 / 114 page

Signal descriptions

M58PR256J, M58PR512J

14/114

Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals

connected to this device.

2.1

Address Inputs (A0-Amax)

Amax is the highest order Address Input. Amax is A23 in the M58PR256J, and A24 in the

M58PR512J. The Address Inputs select the cells in the memory array to access during Bus

Read operations. During Bus Write operations they control the commands sent to the

Command Interface of the Program/Erase Controller.

2.2

Data Input/Output (DQ0-DQ15)

The Data I/O output the data stored at the selected address during a Bus Read operation or

input a command or the data to be programmed during a Bus Write operation.

2.3

Chip Enable (E)

The Chip Enable input activates the memory control logic, input buffers, decoders and

sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active

mode. When Chip Enable is at VIH the memory is deselected, the outputs are high

impedance and the power consumption is reduced to the stand-by level.

2.4

Output Enable (G)

The Output Enable input controls data outputs during the Bus Read operation of the

memory.

2.5

Write Enable (W)

The Write Enable input controls the Bus Write operation of the memory’s Command

Interface. The data and address inputs are latched on the rising edge of Chip Enable or

Write Enable whichever occurs first.

2.6

Write Protect (WP)

Write Protect is an input that gives an additional hardware protection for each Block. When

Write Protect is at VIL, the Lock-Down is enabled and the protection status of the Locked-

Down Blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled

and the Locked-Down Blocks can be locked or unlocked. (refer to Table 21: Lock status).

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