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SPSB100 Fiches technique(PDF) 4 Page - STMicroelectronics |
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SPSB100 Fiches technique(HTML) 4 Page - STMicroelectronics |
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4 / 214 page ![]() 1.2 Pin description Figure 2. Pin connection (top view) 1 56 SGND CSN SDO SDI CLK NRST VIO VS WU DLB VREG FIN1 NFSO1 FB1 LDO2 GBY LDO1 FBB FB2 IRQ IGN SWDBG GND OUT_HS N.C. N.C. N.C. N.C. Table 1. Pin function # Name Description I/O type 1 FB2 BUCK2 feedback voltage (to internal voltage monitors) I 2 LDO2 Voltage regulator 5 V/3.3 V - tracker of BUCKs output (supply for microcontroller) O 3 LDO1 5 V voltage regulator 1 output O 4 VREG 3.3 V regulator output for BUCK bootstrap O 5 GND DS monitoring ground - 6 N.C.(1) Not connected - 7 N.C.(1) Not connected - 8 GBY Gate driver of external MOS bypass BOOST O 9 FBB BOOST feedback pin and supply for LDO1 and LDO2, OUT_HS, VREG, WU and IGN blocks I 10 VS Boost input I 11 OUT_HS High-side-driver output to supply contacts O 12 WU Wake-up input for static or cyclic monitoring of external contact I 13 IGN Wake-up input for static or cyclic monitoring of external contact with KL15 feature I 14 DLB Drain monitoring of external low-side MOS of BOOST I SPSB100 Block diagram and pin description DS14640 - Rev 1 page 4/214 |
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